Estimation of Path Loss at Wireless Network using WiMax Technology

Authors:DOKI SAIRAM, G.V.SRIDHAR

0001-0007

Implementation of VLSI Architecture for Signed-Unsigned High Speed Booth Multiplier

Authors:P.AVINASH, S.DEEPIKA

0008-0017

Speed Optimized Implementation of 32 Bit RISC (MIPS) Architecture

Authors:KURAMANA HARIKA, SOLOMON J V GOTHAM

0018-0025

VHDL implementation of Latency and Memory Optimized Error Detection and Data Recovery Design

Authors:JAKKALA MOHANA KRISHNA, P.DEEPTHI

0026-0032

Lossless Implementation of Majority Logic Fault Detection Architecture for Memory Applications

Authors:RAZIA BEGUM, D.POTHU RAJU

0033-0040

SOC Implementation of Home Automation System based on RF Module

Authors:CHANDRA SEKHAR RAYI, DR. R.V.KRISHNAIAH

0041-0047

High-Speed FPGA Implementation for DWT of Lifting Scheme

Authors:S.V.SATYA SAI KUMAR, P.SREENIVASULU

0048-0055

Modeling and Simulation of Multi-Operation Microcode based Built-In Self Test for Memory Fault Detection and Repair

Authors:CH. MALLIKHARJUNA REDDY, P.NAVITHA, E.N.V.PURNA CHANDRA RAO

0056-0063

A High Bit Rate Serial-Serial Multiplier with on the Fly Accumulation by Asynchronous Counters

Authors:M. PRATHAP, P.NAVITHA, E.N.V.PURNA CHANDRA RAO

0064-0069

Characterizing the Security Implications of Third-Party Emergency Alert Systems over Cellular Text Messaging Services

Authors:V. AJAY KUMAR1, S. V. SRINIVASA RAJU, B. RAJASEKHARA REDDY

0070-0079